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EL5132, EL5133
Data Sheet May 4, 2007 FN7382.8
670MHz Low Noise Amplifiers
The EL5132 and EL5133 are ultra-low voltage noise, high speed voltage feedback amplifiers that are ideal for applications requiring low voltage noise, including communications and imaging. These devices offer extremely low power consumption for exceptional noise performance. Stable at gains as low as 10, these devices offer 120mA of drive performance. Not only do these devices find perfect application in high gain applications, they maintain their performance down to lower gain settings. These amplifiers are available in small package options (SOT-23) as well as the industry-standard SOIC packages. All parts are specified for operation over the -40C to +85C temperature range.
Features
* 670MHz -3dB bandwidth * Ultra low noise 0.9nV/Hz * 1000V/s slew rate * Low supply current = 12mA * Single supplies from 5V to 12V * Dual supplies from 2.5V to 6V * Fast disable on the EL5132 * Pb-free plus anneal available (RoHS compliant)
Applications
* Pre-amplifier * Receiver
Pinout
EL5132 (8 LD SOIC) TOP VIEW
NC 1 IN- 2 IN+ 3 VS- 4 + 8 CE 7 VS+ 6 OUT 5 NC
* Filter * IF and baseband amplifier * ADC drivers * DAC buffers * Instrumentation * Communications devices
EL5133 (5 LD SOT-23) TOP VIEW
OUT 1 VS- 2 IN+ 3 5 VS+
+4 IN-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5132, EL5133 Ordering Information
PART NUMBER EL5132IS EL5132IS-T7 EL5132IS-T13 EL5132ISZ (Note) EL5132ISZ-T7 (Note) EL5132ISZ-T13 (Note) EL5133IW-T7 EL5133IW-T7A EL5133IWZ EL5133IWZ-T7 (Note) EL5133IWZ-T7A (Note) part marking 5132IS 5132IS 5132IS 5132ISZ 5132ISZ 5132ISZ BCAA BCAA BSAA BSAA BSAA TAPE AND REEL 7" 13" 7" 13" 7" (3k pcs) 7" (250 pcs) 7" (3k pcs) 7" (250 pcs) PACKAGE 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) 5 Ld SOT-23 5 Ld SOT-23 5 Ld SOT-23 (Pb-free) 5 Ld SOT-23 (Pb-free) 5 Ld SOT-23 (Pb-free) PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0038 MDP0038 MDP0038 MDP0038 MDP0038
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN7382.8 May 4, 2007
EL5132, EL5133
Absolute Maximum Ratings (TA = +25C)
Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . 13.2V Slewrate between VS+ and VS- . . . . . . . . . . . . . . . . . . . . . . . . 1V/s IIN-, IIN+, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +125C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER VOS TCVOS IB IOS TCIOS PSRR CMRR CMIR RIN CIN IS AVOL VO ISC BW BW GBWP PM SR tR, tF OS tS dG dP eN iN tEN tDIS VIHCE VILCE IS-OFF IIL-CE IIH-CE Offset Voltage
VS+ = +5V, VS- = -5V, RL = 500, RF = 900, RG = 100, TA = +25C, unless otherwise specified. CONDITIONS MIN -1 Measured from TMIN to TMAX VIN = 0V VIN = 0V Measured from TMIN to TMAX VS+ = 4.75V to 5.25V VIN = 3.0 V Guaranteed by CMRR test Common mode 75 80 3 2 8 -1250 TYP 0.5 0.8 12 400 3 87 100 3.3 5 2 9.2 VOUT = 2.5V, RL = 1k to GND RF = 900, RG = 100, RL = 150 RL = 10 RF = 225, AV = +10, RL = 1k RF = 225, AV = +10, RL = 1k RL = 1k, CL = 6pF RL = 100, VOUT = 2.5V 0.1VSTEP 0.1VSTEP RF = 1k, RLoad = 150 RF = 1k, RLoad = 150 f = 10kHz f = 10kHz 700 5 3.1 70 11 8.5 3.5 140 670 90 3000 55 1000 2.0 10 6.6 0.01 0.01 0.9 3.5 13 20 +1250 MAX 1 UNIT mV V/C A nA nA/C dB dB V M pF mA KV/V V mA MHz MHz MHz V/s ns % ns % nV/Hz pA/Hz
DESCRIPTION
Offset Voltage Temperature Coefficient Input Bias Current Input Offset Current Input Bias Current Temperature Coefficient Power Supply Rejection Ratio Common Mode Rejection Ratio Common Mode Input Range Input Resistance Input Capacitance Supply Current Open Loop Gain Output Voltage Swing Short Circuit Current -3dB Bandwidth 0.1dB Bandwidth Gain Bandwidth Product Phase Margin Slew Rate Rise Time, Fall Time Overshoot 0.01% Settling Time Differential Gain Differential Phase Input Noise Voltage Input Noise Current
ENABLE (EL5132 Only) Enable Time Disable Time
CE Input High Voltage for Power-down CE Input Low Voltage for Power-up
220 175 VS+ - 1 VS+ - 3 No Load, CE = 4V
CE = VSCE = VS+
nS nS V V A A A
Supply Current - Disabled
CE Pin Input Low Current CE Pin Input High Current
13 -1 0 14
25 1 25
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FN7382.8 May 4, 2007
EL5132, EL5133 Typical Performance Curves
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 100k 1M 10M 100M 1G PHASE VS = 5V AV = +10 RG = 25 RL = 500 CL = +1pF 300 240 180 GAIN 120 60 0 -60 -120 -180 -240 -300 FREQUENCY (Hz) PHASE () NORMALIZED GAIN (dB) 5 4 3 2 1 0 -1 -2 -3 -4 -5 100k 1M -3dB BW @ 700MHz 10M 100M FREQUENCY (Hz) 1G
FIGURE 1. GAIN & PHASE vs FREQUENCY
FIGURE 2. -3dB BANDWIDTH
0.5 0.4 NORMALIZED GAIN (dB) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 100k 10M FREQUENCY (Hz) 100M 0.1dB BW @ 30MHz NORMALIZED GAIN (dB)
5 4 3 2 1 0 -1 -2 -3 -4
VS = 5V RG = 25 RL = 500 CL = +1pF
AV = +10
AV = +30 AV = +20 1M 10M 100M FREQUENCY (Hz) 1G
-5 100k
FIGURE 3. 0.1dB BANDWIDTH
FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS +AV
VS = 5V RL = 500
GAIN-BANDWIDTH PRODUCT (MHz)
70 60 GAIN (dB) 50
4000 3500 3000 2500 2000 1500 1000 3.0 VS = 5V RL = 500
40 30 FREQUENCY = 31.6MHz GAIN = 40dB or 100 GAIN BW PRODUCT = 31.6 x 100 = 3160MHz 10.0 FREQUENCY (MHz) 100.0
20 1.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGES (V)
FIGURE 5. GAIN BANDWIDTH PRODUCT
FIGURE 6. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGES
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FN7382.8 May 4, 2007
EL5132, EL5133 Typical Performance Curves (Continued)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 100k 1M 10M FREQUENCY (Hz) VS = 6 VS = 5V VS = 3V VS = 2.5V 100M 1G AV = +10 RG = 25 RL = 500 CL = +1pF 5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 100k 1M 10M RL=100 RL=150 RL=500 100M 1G VS=4 VS = 5V AV = +10 RG = 25 CL = +1pF
RL = 1k
FREQUENCY (Hz)
FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS VS
FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +10)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4
NORMALIZED GAIN (dB)
VS = 5V AV = +20 RG = 25 CL = +1pF RL=1k
5 4 3 2 1 0 -1 -2 -3 -4 1G -5 100k 1M 10M FREQUENCY (Hz) 100M 1G CL= 1pF VS = 5V AV = +10 RG = 25 RF = 225 RL = 500 CL=3.3pF CL=6.8pF CL= 12pF
RL=500 RL=150 RL=100 1M 10M 100M FREQUENCY (Hz)
-5 100k
FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +20)
FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +10)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 100k 1M 10M 100M FREQUENCY (Hz) 1G CL=1pF CL= 23pF CL= 12pF NORMALIZED GAIN (dB) VS = 5V AV = +20 RG = 25 RF = 475 RL = 500 CL=39pF
5 4 3 2 1 0 -1 -2 -3 -4
VS = 5V AV = +10 RL = 500 CL = +1pF
RF = 900 RF = 450
RF = 90 RF = 225 1M 10M FREQUENCY (Hz) 100M 1G
-5 100k
FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +20)
FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +10)
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FN7382.8 May 4, 2007
EL5132, EL5133 Typical Performance Curves (Continued)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 100k 1M 10M FREQUENCY (Hz) RF = 953 RF = 190 RF = 475 100M 1G NORMALIZED GAIN (dB) VS = 5V AV = +20 RL = 500 CL = +1pF 5 4 3 2 1 0 -1 -2 -3 -4 -5 100k 1M 10M 100M FREQUENCY (Hz) 1G CIN = 2.2pF CIN = 0pF RF = 1.9k VS = 5V AV = +10 RG = 25 RL = 500 CL = +1pF CIN = 6.8pF CIN = 3.9pF
FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +20)
FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS CIN(-) (AV = +10)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 100k 1M CIN = 0pF 10M 100M FREQUENCY (Hz) 1G CIN = 8.2pF OPEN LOOP GAIN (dB) VS = 5V AV = +20 RG = 25 RL = 500 CL = +1pF CIN = 22pF CIN = 15pF CIN = 12pF
90 80 70 60 50 40 30 20 10 0 -10 1k
Vs = 5V
300 240 180 120 60 PHASE ()
OPEN LOOP PHASE
0 -60 -120 -180 -240 -300
OPEN LOOP GAIN
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS CIN (AV = +20)
FIGURE 16. OPEN LOOP GAIN AND PHASE vs FREQUENCY
100 VS = 5V OUTPUT IMPEDANCE () 10 CMRR (dB)
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 AV = +10 VS = 5V
1
0.10
0.01 10k
100k
1M
10M
100M
-110 1k
10k
100k
1M
10M
100M 500M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 17. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 18. CMRR vs FREQUENCY
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FN7382.8 May 4, 2007
EL5132, EL5133 Typical Performance Curves (Continued)
10 OUTPUT SWING GAIN (dB) 0 -10 PSRR (dB) -20 -30 -40 -50 -60 -70 -80 -90 1k 10k 100k VS+ 1M 10M 100M 500M VSAV = +10 VS = 5V 5 4 3 2 1 0 -1 -2 -3 -4 -5 1M FREQUENCY (Hz) VOUT = 670mVP-P VOUT = 2.1VP-P VOUT = 3.8VP-P VOUT = 6.6VP-P 10M 100M FREQUENCY (Hz) 1G VS = 5V AV = +10 RG = 25 RL = 500 CL = +1pF
VOUT = 240mVP-P
FIGURE 19. PSRR vs FREQUENCY
FIGURE 20. OUTPUT SWING vs FREQUENCY
20 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 0
GROUP DELAY (ns)
ISOLATION (dB)
VS = 5V AV = +10 RG = 25 RL = 500
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 1M 10M FREQUENCY (Hz) 100M 1G -140 100k 1M 10M 100M VS = 5V AV = +20 RG = 25 CHIP DISABLED INPUT TO OUTPUT OUTPUT TO INPUT
FREQUENCY (Hz)
FIGURE 21. GROUP DELAY vs FREQUENCY
FIGURE 22. INPUT AND OUTPUT ISOLATION
-30 HARMONIC DISTORTION (dBc) THD HARMONIC DISTORTION (dBc) VS = 5V -40 AV = +10 RG = 25 -50 RL = 500 VOUT = 2VP-P -60 -70 -80 -90 -100 0M 5M 10M 15M 20M 25M 30M 35M 40M FUNDAMENTAL FREQUENCY (Hz) 2nd HD 3rd HD
-20 -30 -40 -50 -60 -70 -80 -90 -100 0
VS = 5V AV = +10 RG = 25 RL = 500
FIN = 10MHz
FIN = 1MHz 1 2 3 4 5 6 OUTPUT LEVEL (VP-P) 7 8
FIGURE 23. HARMONIC DISTORTION vs FREQUENCY
FIGURE 24. TOTAL HARMONIC DISTORTION vs OUTPUT VOLTAGE
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FN7382.8 May 4, 2007
EL5132, EL5133 Typical Performance Curves (Continued)
6 5 4 AMPLITUDE (V) 3 2 1 0 -1 -2 -3 -400 -200 0 OUTPUT SIGNAL 200 400 600 800 1000 1200 VS = 5V RL = 500 VOUT = 2VP-P AMPLITUDE (V) ENABLE SIGNAL 6 5 4 3 OUTPUT SIGNAL 2 1 0 -1 -2 -1000 -800 -600 -400 -200 0 TIME (ns) 200 400 600 VS = 5V RL = 500 VOUT = 2VP-P DISABLE SIGNAL
TIME (ns)
FIGURE 25. ENABLE TIME
FIGURE 26. DISABLE TIME
100.0 VOLTAGE NOISE (nV/Hz)
VS = 5V CURRENT NOISE (pA/Hz)
1000.0
VS = 5V
10.0
100.0
1.0
10.0
0.1
1.0
0.0 10
0.1 100 1k 10k FREQUENCY (Hz) 100k 1M 10 100 1k 10k 100k FREQUENCY (Hz) 1M
FIGURE 27. EQUIVALENT INPUT VOLTAGE NOISE vs FREQUENCY
FIGURE 28. EQUIVALENT INPUT CURRENT NOISE vs FREQUENCY
0.4
2.0
AMPLITUDE (V)
AMPLITUDE (V)
0.2 TFALL= 2.02ns 0.0 TRISE = 2.12ns -0.2 VS = 5V RL = 500 AV = +10 CL = +1pF RG = 25 VOUT = 500mV 20 40 60 80 100 120 140 160 180 TIME (ns)
1.0 TFALL = 2.05ns 0.0 TRISE = 2.02ns -1.0 VS = 5V RL = 500 AV = +10 CL = 1pF RG = 25 VOUT = 2.0V 20 40 60 80 100 120 140 160 180 TIME (ns)
-0.4 -40 -20 0
-2.0 -40 -20 0
FIGURE 29. SMALL SIGNAL STEP RESPONSE_RISE AND FALL TIME
FIGURE 30. LARGE SIGNAL STEP RESPONSE_RISE AND FALL TIME
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FN7382.8 May 4, 2007
EL5132, EL5133 Typical Performance Curves (Continued)
12.0 SUPPLY CURRENT (mA) 11.8 11.6 11.4 11.2 11.0 10.8 10.6 10.4 10.2 10.0 2.5 3.0 Please note that the curve showed positive current. The negative current was almost the same. 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 RG = 25 RL = 500 CL = +1pF SLEW RATE (V/s) 1200 1100 1000 900 800 700 600 500 400 300 2.0 2.5 AV = +10 RG = 25 RL = 500 CL = +1pF VOUT = 4VP-P 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGES (V) 5.5 6.0 NEGATIVE SLEW RATE POSITIVE SLEW RATE
FIGURE 31. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 32. SLEW RATE vs SUPPLY VOLTAGES
1.4 POWER DISSIPATION (W) 1.2
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSIPATION (W)
1 0.9 0.8
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
1 909mW 0.8 0.6 0.4 0.2 0 0 25 435mW
SO8 JA = +110C/W
0.7 625mW 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) SOT23-5 JA = +256C/W 391mW SO8 JA = +160C/W
SOT23-5 JA = +230C/W 50 75 85 100 125 150
AMBIENT TEMPERATURE (C)
FIGURE 33. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 34. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7382.8 May 4, 2007
EL5132, EL5133 Typical Performance Curves (Continued)
DIFFERENTIAL GAIN (%) 0.2 0.1 0.0 0 -0.05 -0.15 -0.20 0 10 20 30 40 50 60 70 80 90 100
FIGURE 35. DIFFERENTIAL GAIN (%)
DIFFERENTIAL PHASE ()
0.20 0.15 0.05 0 -0.05 -0.15 -0.20 0 10 20 30 40 50 60 70 80 90 100
FIGURE 36. DIFFERENTIAL PHASE ()
Applications Information
Product Description
The EL5132, EL5133 is a voltage feedback operational amplifier designed for communication and imaging applications requiring very low voltage and current noise. It also features low distortion while drawing moderately low supply current and is built on Intersil's proprietary high-speed complementary bipolar process. The EL5132, EL5133 uses a classical voltage-feedback topology which allows them to be used in a variety of applications where current-feedback amplifiers are not appropriate because of restrictions placed upon the feedback element used with the amplifier.
Output Drive Capability
The EL5132 and EL5133 are is designed to drive a low impedance load. It can easily drive 6VP-P signal into a 500 load. This high output drive capability makes the EL5132, EL5133 an ideal choice for RF, IF, and video applications. Furthermore, the EL5132, EL5133 is current-limited at the output, allowing it to withstand momentary short to ground. However, the power dissipation with output-shorted cannot exceed the power dissipation capability of the package.
Driving Cables and Capacitive Loads
Although the EL5132, EL5133 is designed to drive low impedance load, capacitive loads will decreases the amplifier's phase margin. As shown in the performance curves, capacitive load can result in peaking, overshoot and possible oscillation. For optimum AC performance, capacitive loads should be reduced as much as possible or isolated with a series resistor between 5 to 20. When driving coaxial cables, double termination is always recommended for reflection-free performance. When properly terminated, the capacitance of the coaxial cable will not add to the capacitive load seen by the amplifier.
Gain-Bandwidth Product and the -3dB Bandwidth
The EL5132, EL5133 has a gain-bandwidth product of 3000MHz while using only 11mA of supply current. For gains greater than 10, their closed-loop -3dB bandwidth is approximately equal to the gain-bandwidth product divided by the noise gain of the circuit. For gains of 10, higher-order poles in the amplifiers' transfer function contribute to even higher closed loop bandwidths. For example, the EL5132, EL5133 have a -3dB bandwidth of 670MHz at a gain of 10, dropping to 150MHz at a gain of 30. It is important to note that the EL5132, EL5133 is designed so that this "extra" bandwidth in low-gain application does not come at the expense of stability. As seen in the typical performance curves, the EL5132, EL5133 in a gain of only 10 exhibited 0.5dB of peaking with a 500 load.
Disable/Power-Down
The EL5132 amplifier can be disabled placing its output in a high impedance state. When disable, the amplifier current is reduced to 12A. The EL5132 is disabled when it CE pin is pulled up to within 1V of the power supply. Similarly, the amplifier is enabled by floating or pulling its CE pin to at least 3V below the positive supply. For 5V supply, this means that an EL5132 amplifier will be enabled when CE is 2V or
10
FN7382.8 May 4, 2007
EL5132, EL5133
less, and disabled when CE is above 4V. Although the logic levels are not standard TTL, this choice of logic voltages allows the EL5132 to be enabled by typing CE to ground, even in 5V single supply applications. The CE pin can be driving from CMOS outputs. where: * TMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation of 1 amplifier * VS = Supply voltage * IMAX = Maximum supply current of 1 amplifier * VOUTMAX = Maximum output voltage swing of the application * RL = Load resistance
Supply Voltage Range and Single-Supply Operation
The EL5132 and EL5133 have been designed to operate with supply voltages having a span of greater than 5V and less than 12V. In practical terms, this means that they will operate on dual supplies ranging from 2.5V to 6V. With single-supply, the EL5132 and EL5133 will operate from 5V to 12V. To prevent internal circuit latch-up, the slew rate between the negative and positve supplies must be less than 1V/s. As supply voltages continue to decrease, it becomes necessary to provide input and output voltage ranges that can get as close as possible to the supply voltages. The EL5132 and EL5133 have an input range which extends to within 2V of either supply. So, for example, on 5V supplies, the EL5132 and EL5133 have an input range which spans 3V. The output range of the EL5132 and EL5133 are also quite large, extending to within 2V of the supply rail. On a 5V supply, the output is therefore capable of swinging from -3.1V to +3.1V. Single-supply output range is larger because of the increased negative swing due to the external pulldown resistor to ground.
Power Supply Bypassing And Printed Circuit Board Layout
As with any high frequency devices, good printed circuit board layout is essential for optimum performance. Ground plane construction is highly recommended. Pin lengths should be kept as short as possible. The power supply pins must be closely bypassed to reduce the risk of oscillation. The combination of a 4.7F tantalum capacitor in parallel with 0.1F ceramic capacitor has been proven to work well when placed at each supply pin. For single supply operation, where pin 4 (VS-) is connected to the ground plane, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic capacitor across pin 8 (VS+). For good AC performance, parasitic capacitance should be kept to a minimum. Ground plane construction again should be used. Small chip resistors are recommended to minimize series inductance. Use of sockets should be avoided since they add parasitic inductance and capacitance which will result in additional peaking and overshoot.
Power Dissipation
With the wide power supply range and large output drive capability of the EL5132 and EL5133, it is possible to exceed the 150C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified for the EL5132 and EL5133 to remain in the safe operating area. These parameters are related as follows:
T JMAX = T MAX + ( JA xPD MAXTOTAL ) (EQ. 1)
where: * PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) * PDMAX for each amplifier can be calculated as follows:
V OUTMAX PD MAX = 2*V S x I SMAX + ( V S - V OUTMAX ) x --------------------------R (EQ. 2)
L
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FN7382.8 May 4, 2007
EL5132, EL5133 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
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FN7382.8 May 4, 2007
EL5132, EL5133 SOT-23 Package Family
e1 A N 6 4
MDP0038
D
SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. F 2/07 NOTES:
E1 2 3
E
A2 b c
0.20 C
0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D
D E E1 e e1 L L1 N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only).
(L1)
H
6. SOT23-5 version has no center lead (shown as a dashed line).
A
GAUGE PLANE c L 0 +3 -0
0.25
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN7382.8 May 4, 2007

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